Accelerating Boolean Constraint Propagation for Efficient SAT-Solving on FPGAs. Proceedings of the Great Lakes Symposium on VLSI 2024. https://doi.org/10.1145/3649476.3658808
Chicago Style (17th ed.) Citation"Accelerating Boolean Constraint Propagation for Efficient SAT-Solving on FPGAs." Proceedings of the Great Lakes Symposium on VLSI 2024 . https://doi.org/10.1145/3649476.3658808.
MLA (9th ed.) Citation"Accelerating Boolean Constraint Propagation for Efficient SAT-Solving on FPGAs." Proceedings of the Great Lakes Symposium on VLSI 2024, , https://doi.org/10.1145/3649476.3658808.
Warning: These citations may not always be 100% accurate.