APA (7th ed.) Citation

Manerkar, Y. A., Lustig, D., Martonosi, M., & Pellauer, M. (2017, October 14). RTLcheck: Verifying the memory consistency of RTL designs. MICRO-50 : the 50th annual IEEE/ACM International Symposium on Microarchitecture : proceedings : October 14-18, 2017, Cambridge, MA, 463-476. https://doi.org/10.1145/3123939.3124536

Chicago Style (17th ed.) Citation

Manerkar, Yatin A., Daniel Lustig, Margaret Martonosi, and Michael Pellauer. "RTLcheck: Verifying the Memory Consistency of RTL Designs." MICRO-50 : The 50th Annual IEEE/ACM International Symposium on Microarchitecture : Proceedings : October 14-18, 2017, Cambridge, MA 14 Oct. 2017: 463-476. https://doi.org/10.1145/3123939.3124536.

MLA (9th ed.) Citation

Manerkar, Yatin A., et al. "RTLcheck: Verifying the Memory Consistency of RTL Designs." MICRO-50 : The 50th Annual IEEE/ACM International Symposium on Microarchitecture : Proceedings : October 14-18, 2017, Cambridge, MA, 14 Oct. 2017, pp. 463-476, https://doi.org/10.1145/3123939.3124536.