Circuit techniques for dynamic variation tolerance

• Published in: 2009 46th ACM/IEEE Design Automation Conference pp. 4 - 7
• Main Authors: Bowman, Keith, Tschanz, James, Wilkerson, Chris, Lu, Shih-Lien, Karnik, Tanay, De, Vivek, Borkar, Shekhar
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 26.07.2009; IEEE
• Series: ACM Conferences
• Subjects: Aging; Circuits; Degradation; Delay; Dynamic variations; Energy efficiency; Error correction; error detection; error recovery; error-detection sequential; Frequency; Hardware > Emerging technologies; Hardware > Very large scale integration design; Microprocessors; parameter variations; Permission; replica paths; resilient circuits; Temperature; timing errors; variation sensors; variation-tolerant circuits; parameter variations; resilient circuits; dynamic variations; error recovery; variation sensors; variation-tolerant circuits; replica paths; timing errors; error-detection sequential; error detection; error correction
• ISBN: 9781605584973; 1605584975
• ISSN: 0738-100X
• DOI: 10.1145/1629911.1629915

Three circuit techniques for dynamic variation tolerance are presented: (i) Sensors with adaptive voltage and frequency circuits, (ii) Tunable replica circuits for timing-error prediction with error recovery, and (iii) Embedded error-detection sequential circuits with error recovery. These circuits mitigate the clock frequency guardbands for dynamic variations, thus improving microprocessor performance and energy-efficiency. These circuits are described with a focus on the different trade-offs in guardband reduction and design overhead. Opportunities for CAD to further enhance microprocessor performance and energy efficiency are offered.