Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling

• Published in: 2003 40th Annual Conference Design Automation pp. 169 - 174
• Main Authors: Mukhopadhyay, Saibal, Raychowdhury, Arijit, Roy, Kaushik
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 02.06.2003; IEEE
• Series: ACM Conferences
• Subjects: CMOS logic circuits; Doping profiles; Geometry; Hardware > Hardware validation > Functional verification > Simulation and emulation; Leakage current; Logic circuits; Semiconductor device modeling; Semiconductor process modeling; Solid modeling; Temperature; Tunneling; tunneling; doping profiles; threshold voltage; leakage
• ISBN: 1581136889; 9781581136883
• DOI: 10.1145/775832.775877

Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage in scaled devices, results in the drastic increase of total leakage power in a logic circuit. In this paper a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in scaled devices has been developed. Current models have been developed based on the exact device geometry, 2-D doping profile and operating temperature. A circuit level model of junction BTBT leakage (which is unprecedented) has been developed. Simple models of the subthreshold current and the gate current have been presented. Here, for the first time, the impact of quantum mechanical behavior of substrate electrons, on the circuit leakage has been analyzed. Using the compact current model, a transistor has been modeled as a Sum of Current Sources (SCS). The SCS transistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25nm effective length) at the room and at the elevated temperatures.