APA (7th ed.) Citation

Mukhopadhyay, S., Raychowdhury, A., & Roy, K. (2003, June 2). Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. 2003 40th Annual Conference Design Automation, 169-174. https://doi.org/10.1145/775832.775877

Chicago Style (17th ed.) Citation

Mukhopadhyay, Saibal, Arijit Raychowdhury, and Kaushik Roy. "Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling." 2003 40th Annual Conference Design Automation 2 Jun. 2003: 169-174. https://doi.org/10.1145/775832.775877.

MLA (9th ed.) Citation

Mukhopadhyay, Saibal, et al. "Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling." 2003 40th Annual Conference Design Automation, 2 Jun. 2003, pp. 169-174, https://doi.org/10.1145/775832.775877.