Advanced VLSI Technology Technical Questions with Solutions

• Main Authors: Bhargava, Cherry, Khanal, Gaurav Mani
• Format: eBook
• Language: English
• Published: Milton River Publishers 01.09.2022
• Edition: 1
• Series: River Publishers Series in Circuits and Systems
• Subjects: Circuits & Devices; Integrated circuits
• ISBN: 877022174X; 9788770221740
• DOI: 10.1201/9781003337065

The trend in design and manufacturing of very large-scale integrated (VLSI) circuits is towards smaller devices on increasing wafer dimensions. VLSI is the inter-disciplinary science of the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI...

Table of Contents:

• Annexure II: List of Keywords, System Tasks, and Compiler Directives Used in Verilog HDL -- Index -- About the Authors
• Cover -- Half Title -- Series -- Title -- Copyright -- Dedication -- Contents -- Preface -- Acknowledgement -- List of Figures -- List of Tables -- List of Abbreviations -- 1 Static Timings Analysis -- 1.1 Timing Components -- 1.1.1 Clock Signal -- 1.1.2 Quartz Crystal -- 1.1.3 Crystal Oscillator -- 1.1.4 Clock Generator -- 1.1.5 Clock Rate -- 1.1.6 Clock Multiplier -- 1.1.7 Clock Tree -- 1.1.8 Clock Phase -- 1.1.9 Clock Gating -- 1.1.10 Clock Jitter -- 1.1.11 Clock Latency -- 1.2 Crosstalk -- 1.2.1 Crosstalk Noise Due To Coupling Capacitance -- 1.2.2 Coupling Capacitance -- 1.3 Static Timing Analysis -- 1.4 Unateness and Its Types -- References -- 2 CMOS Design and Layout -- 2.1 Introduction -- 2.2 CMOS-Design-Flow -- 2.3 Stick Diagram -- 2.3.1 Notations of Stick Diagram -- 2.3.2 Rules to draw stick diagram -- 2.4 Design Rules -- 2.4.1 CMOS Lambda 'λ' Design Rules -- 2.4.1.1 Design Rule Check -- 2.4.2 Micron-Design-Rules -- 2.5 Layout Design Rules -- 2.5.1 Layered Representation of Layout -- References -- 3 Physical Design Automation -- 3.1 Introduction -- 3.2 Types of Cell for Physical Design Automation -- 3.2.1 Well Tap Cells -- 3.2.2 End Cap Cells -- 3.2.3 Decap Cells -- 3.2.4 Spare Cells -- 3.2.5 Filler Cells -- References -- 4 Testing of VLSI Circuits -- 4.1 Introduction -- 4.1.1 Rule of Ten -- 4.2 Testing of a Circuit -- 4.2.1 Testing During VLSI Development -- 4.2.1.1 Yield -- 4.2.2 Design For Test (DFT) -- 4.2.2.1 Automatic Test Pattern Generation (ATPG) -- 4.2.2.2 Defect and Error -- 4.2.3 Fault Model -- 4.2.3.1 Detection of fault -- 4.2.3.2 Phases of fault -- References -- 5 Miscellaneous -- 5.1 Branches of Electronics -- 5.1.1 Electronics and Communication Engineering (ECE) -- 5.1.2 Electronics and Telecommunication Engineering (ETE) -- 5.1.3 Microelectronics and VLSI Design -- References -- Annexure I: Digital Circuit IC Numbers