Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration

• Published in: 2006 43rd ACM/IEEE Design Automation Conference pp. 31 - 36
• Main Authors: Tiwary, Saurabh K., Tiwary, Pragati K., Rutenbar, Rob A.
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 24.07.2006; IEEE
• Series: ACM Conferences
• Subjects: Algorithms Design; Circuit simulation; Circuit synthesis; Circuit topology; Computational modeling; Hardware > Electronic design automation > Physical design (EDA); Monte Carlo methods; optimization; Pareto optimization; pareto surfaces; performance space; Sorting; Space exploration; Space technology; Voltage-controlled oscillators; Yield; performance space; optimization; pareto surfaces; yield
• ISBN: 1595933816; 9781595933812
• ISSN: 0738-100X
• DOI: 10.1145/1146909.1146921

Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulator-in-a-loop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yield-aware pareto fronts. We show experimental results for both the nominal and yield-aware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yield-aware pareto fronts in approximately 5-6 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yield-aware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop.