Simultaneous transistor pairing and placement for CMOS standard cells - Ang Lu; Hsueh-Ju Lu; En-Jang Jang; Yu-Po Lin; Chun-Hsiang Hung; Chun-Chih Chuang; Rung-Bin Lin (2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015)
Keywords: Layout; Logic gates; Runtime; standard cell; transistor folding; transistor pairing; Transistor placement; Transistors; Wires; Wiring