Power mapping and modeling of multi-core processors

• Published in: Proceedings of the 2013 International Symposium on Low Power Electronics and Design pp. 39 - 44
• Main Authors: Dev, Kapil, Nowroz, Abdullah Nazma, Reda, Sherief
• Format: Conference Proceeding
• Language: English
• Published: Piscataway, NJ, USA IEEE Press 04.09.2013
• Series: ACM Conferences
• Subjects: Applied computing > Physical sciences and engineering > Electronics; Computer systems organization > Architectures > Parallel architectures; Hardware > Hardware validation
• ISBN: 1479912352; 9781479912353
• DOI: 10.5555/2648668.2648680

We propose new techniques for post-silicon power mapping and modeling of multi-core processors using infrared imaging and performance counter measurements. An accurate finite-element modeling framework is used to capture the relationship between temperature and power, while compensating for the artifacts introduced from substituting traditional heat removal mechanisms with oil-based infrared-transparent cooling mechanisms. We use thermal conditioning techniques to build leakage power models for the die. Utilizing the power maps identified from infrared mapping, we develop empirical power models for different processor blocks based on the measurements from the performance monitoring counters (PMCs), and utilize the PMC-based models to analyze the transient power consumption. In our experiments, we capture thermal images from a quad-core processor under different workload conditions, and then we reconstruct the dynamic and leakage power maps for different blocks. Our results show good accuracy in mapping and modeling, revealing good insights into the trends of power consumption in multi-core processors.