Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology

• Published in: Proceedings of the 2013 International Symposium on Low Power Electronics and Design pp. 255 - 260
• Main Authors: de Streel, Guerric, Bol, David
• Format: Conference Proceeding
• Language: English
• Published: Piscataway, NJ, USA IEEE Press 04.09.2013
• Series: ACM Conferences
• Subjects: Applied computing > Physical sciences and engineering > Electronics; Hardware > Integrated circuits > Logic circuits; ultra-low-voltage; 28nm; CMOS FDSOI; robustness; back gate biasing; die yield; ultra-low power; subthreshold logic
• ISBN: 1479912352; 9781479912353
• DOI: 10.5555/2648668.2648733

Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of Back Biasing (BB) schemes on these features for FDSOI technology. We show that Forward BB can help cover a wider design space in term of optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on Minimum Energy Point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36X speedup at the MEP.