Synthesis of multiplier-less FIR filters with minimum number of additions

• Published in: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design pp. 668 - 671
• Main Authors: Mehendale, Mahesh, Sherlekar, S. D., Venkatesh, G.
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 01.12.1995
• Series: ACM Conferences
• Subjects: Hardware > Communication hardware, interfaces and storage > Signal processing systems; Hardware > Integrated circuits > Logic circuits > Arithmetic and datapath circuits; FIR filters; low pass FIR filters; MCM based structures; network synthesis; binary representations; circuit CAD; iterative elimination; optimizing transformations
• ISBN: 9780818672132; 0818672137
• DOI: 10.5555/224841.225141

In this paper we present optimizing transformations to minimize the number of additions+subtractions in both the direct form (/spl Sigma/ A/sub i/X/sub n-i/ based) and its transposed form (Multiple Constant Multiplication based) implementation of FIR filters. These transformations are based on the iterative elimination of 2-bit common subexpressions in the coefficients binary representations. We give detailed description of the algorithms and present results for eight low pass FIR filters with the number of coefficients ranging from 16 to 128. The results show upto 35% reduction in the number of additions+subtractions to implement /spl Sigma/ A/sub i/X/sub n-i/ based FIR filter structures and upto 38% reduction to implement MCM based structures.