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An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures
Abe, Shin-ya, Yanagisawa, M., Togawa, N.
Published in 2012 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2012)
Published in 2012 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2012)
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Conference Proceeding
High-Level Synthesis Algorithm for Continuous-Flow Microfiuidic Biochips Under Device Volume Constraints
Chen, Zhengyang, Pan, Youlin, Chen, Zhen, Liu, Genggeng
Published in 2023 International Conference on Computer Science and Automation Technology (CSAT) (06.10.2023)
Published in 2023 International Conference on Computer Science and Automation Technology (CSAT) (06.10.2023)
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Conference Proceeding
A partial redundant fault-secure high-level synthesis algorithm for RDR architectures
Kawamura, Kazushi, Tanaka, Sho, Yanagisawa, Masao, Togawa, Nozomu
Published in 2013 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2013)
Published in 2013 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2013)
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Conference Proceeding
A delay variation and floorplan aware high-level synthesis algorithm with body biasing
Igawa, Koki, Youhua Shi, Yanagisawa, Masao, Togawa, Nozomu
Published in Proceedings / IEEE International Symposium on Quality Electronic Design (01.03.2016)
Published in Proceedings / IEEE International Symposium on Quality Electronic Design (01.03.2016)
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Conference Proceeding
A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures
Igawa, Koki, Youhua Shi, Yanagisawa, Masao, Togawa, Nozomu
Published in Proceedings / IEEE International SOC Conference (01.09.2015)
Published in Proceedings / IEEE International SOC Conference (01.09.2015)
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Conference Proceeding
Journal Article
A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration
Fujiwara, Koichi, Kawamura, Kazushi, Yanagisawa, Masao, Togawa, Nozomu
Published in 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (01.04.2016)
Published in 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (01.04.2016)
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Conference Proceeding
A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration
Terada, Kotaro, Yanagisawa, Masao, Togawa, Nozomu
Published in APCCAS : 2014 IEEE Asia Pacific Conference on Circuits and Systems : 17-20 November 2014 (01.11.2014)
Published in APCCAS : 2014 IEEE Asia Pacific Conference on Circuits and Systems : 17-20 November 2014 (01.11.2014)
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Conference Proceeding
A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs
Fujiwara, Koichi, Abe, Shinya, Kawamura, Kazushi, Yanagisawa, Masao, Togawa, Nozomu
Published in APCCAS : 2014 IEEE Asia Pacific Conference on Circuits and Systems : 17-20 November 2014 (01.11.2014)
Published in APCCAS : 2014 IEEE Asia Pacific Conference on Circuits and Systems : 17-20 November 2014 (01.11.2014)
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Conference Proceeding
A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures
Hagio, Yuta, Yanagisawa, Masao, Togawa, Nozomu
Published in Information and Media Technologies (01.01.2014)
Published in Information and Media Technologies (01.01.2014)
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Journal Article
An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages
Abe, S., Youhua Shi, Usami, K., Yanagisawa, M., Togawa, N.
Published in 2013 International Symposium on VLSI Design, Automation and Test (01.04.2013)
Published in 2013 International Symposium on VLSI Design, Automation and Test (01.04.2013)
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Conference Proceeding
High-level synthesis algorithms with floorplaning for distributed/shared-register architectures
Ohchi, A., Togawa, N., Yanagisawa, M., Ohtsuki, T.
Published in 2008 International Symposiium on VLSI Design, Automation and Test (01.04.2008)
Published in 2008 International Symposiium on VLSI Design, Automation and Test (01.04.2008)
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Conference Proceeding
Cyber-Physical Codesign at the Functional Level for Multidomain Automotive Systems
Jiang Wan, Canedo, Arquimedes, Al Faruque, Mohammad Abdullah
Published in IEEE systems journal (01.12.2017)
Published in IEEE systems journal (01.12.2017)
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Journal Article
Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms
Published in IEICE electronics express
(2016)
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Journal Article