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Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Krishnaswamy, Smita, Viamontes, George F., Markov, Igor L., Hayes, John P.
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
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Conference Proceeding
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Kastensmidt, F. Lima, Sterpone, L., Carro, L., Reorda, M. Sonza
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
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Conference Proceeding
Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives
Bougard, Bruno, Catthoor, Francky, Daly, Denis C., Chandrakasan, Anantha, Dehaene, Wim
Published in Design, Automation and Test in Europe (01.01.2005)
Published in Design, Automation and Test in Europe (01.01.2005)
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Conference Proceeding
Top-Down System Level Design Methodology Using SpecC, VCC and SystemC
Cai, L., Gajski, D., Kritzinger, P., Olivares, M.
Published in Proceedings of the conference on Design, automation and test in Europe (04.03.2002)
Published in Proceedings of the conference on Design, automation and test in Europe (04.03.2002)
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Conference Proceeding
Speeding up SAT for EDA
Pilarski, S., Hu, G.
Published in Proceedings of the conference on Design, automation and test in Europe (04.03.2002)
Published in Proceedings of the conference on Design, automation and test in Europe (04.03.2002)
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Conference Proceeding
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification
Goossens, Kees, Dielissen, John, Gangwal, Om Prakash, Pestana, Santiago Gonzalez, Radulescu, Andrei, Rijpkema, Edwin
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
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Conference Proceeding
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach
Yang, Shengqi, Wolf, Wayne, Vijaykrishnan, N., Serpanos, D. N., Xie, Yuan
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
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Conference Proceeding
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
Vazquez, P., Juan-Chico, J., Bellido, M., Acosta, A., Valencia, M.
Published in Proceedings of the conference on Design, automation and test in Europe (13.03.2001)
Published in Proceedings of the conference on Design, automation and test in Europe (13.03.2001)
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Conference Proceeding
Modelling SoC devices for virtual test using VHDL
Rona, M., Krampl, G.
Published in Proceedings of the conference on Design, automation and test in Europe (13.03.2001)
Published in Proceedings of the conference on Design, automation and test in Europe (13.03.2001)
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Conference Proceeding
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring
Arora, Divya, Ravi, Srivaths, Raghunathan, Anand, Jha, Niraj K.
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
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Conference Proceeding
Quantum Circuit Simplification Using Templates
Maslov, D., Young, C., Miller, D. M., Dueck, G. W.
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
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Conference Proceeding
Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications
Zhang, Lintao, Malik, Sharad
Published in Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003 (03.03.2003)
Published in Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003 (03.03.2003)
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Conference Proceeding
An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor
Yang, Chuan-Yue, Chen, Jian-Jia, Kuo, Tei-Wei
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
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Conference Proceeding
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Dhillon, Yuvraj Singh, Diril, Abdulkadir Utku, Chatterjee, Abhijit
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
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Conference Proceeding
A Complete Network-On-Chip Emulation Framework
Genko, N., Atienza, D., Micheli, G. De, Mendias, J. M., Hermida, R., Catthoor, F.
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
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Conference Proceeding
Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems
Izosimov, Viacheslav, Pop, Paul, Eles, Petru, Peng, Zebo
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
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Conference Proceeding
A Synthesizable IP Core for DVB-S2 LDPC Code Decoding
Kienle, Frank, Brack, Torben, Wehn, Norbert
Published in Design, Automation and Test in Europe (01.01.2005)
Published in Design, Automation and Test in Europe (01.01.2005)
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Conference Proceeding
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms
Kempf, Torsten, Doerper, Malte, Leupers, R., Ascheid, G., Meyr, H., Kogel, Tim, Vanthournout, Bart
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
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Conference Proceeding