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Gridless Gap Channel Routing to Minimize Wirelength
Shimoda, Masayuki, Takahashi, Atsushi
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2025)
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2025)
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Journal Article
1W8R 20T SRAM Codebook for 20% Energy Reduction in Mixed-precision Deep-learning Inference Processor System
Masaya, Kabuto, Yasuda, Yuto, Izumi, Shintaro, Kawaguchi, Hiroshi, Hamabe, Riku, Fukunaga, Atsushi, Taichi, Masakazu, Ohara, Ryotaro
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2025)
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2025)
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Journal Article
Proposal for Non-Volatilization of Logic Cell Architecture for eFPGA IP
Iida, Masahiro, Seto, Kenshu, Hiraga, Keizo, Bessho, Kazuhiro
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2025)
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2025)
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Journal Article
A Learning-based Control Scheme for MTJ-based Non-volatile Flip-Flops
Nakabeppu, Shota, Yamasaki, Nobuyuki
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)
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Journal Article
Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration
Knechtel, Johann, Sze, Cliff C. N., Elfadel, Ibrahim (Abe) M., Lienig, Jens, Sinanoglu, Ozgur
Published in IPSJ Transactions on System LSI Design Methodology (01.01.2017)
Published in IPSJ Transactions on System LSI Design Methodology (01.01.2017)
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Journal Article
Design of Synthesizable Digital Phase Locked Loops
Zhang, Yuncheng, Okada, Kenichi
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)
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Journal Article
Power Optimized Design Framework for FPGA Clusters
Yasudo, Ryota, Iizuka, Kensuke, Ito, Kohei, Amano, Hideharu
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)
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Journal Article
A Case Study for Improving Performances of Deep-Learning Processor with MRAM
Ikegawa, Masato, Taichi, Masakazu, Kawaguchi, Hiroshi, Hamabe, Riku, Fukunaga, Atsushi, Kabuto, Masaya, Ohara, Ryotaro, Izumi, Shintaro
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)
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Journal Article
A Low-Power Reconfigurable DNN Accelerator for Instruction-Extended RISC-V
Li, Dongju, Wang, Hansen, Isshiki, Tsuyoshi
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)
Published in IPSJ Transactions on System and LSI Design Methodology (01.01.2024)
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Journal Article