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A new systolic architecture for pipeline prime factor DFT-algorithm
Sedukhin, S.G.
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (17.12.2002)
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (17.12.2002)
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Conference Proceeding
Convergence analyses of simulated evolution algorithms
Chi-Yu Mao, Yu Hen Hu
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
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Conference Proceeding
Design of a 54-bit adder using a modified Manchester carry chain
Hashemian, R.
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
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Conference Proceeding
Retiming algorithms with application to VLSI testability
Kagaris, D., Tragoudas, S.
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
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Conference Proceeding
Scaling of serially-connected MOSFET chains
Vemuru, S.R.
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
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Conference Proceeding
FPGA-based synthesis of FSMs through decomposition
Yang, W.L., Owen, R.M., Irwin, M.J.
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
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Conference Proceeding
A distributed controller for system level integration
Vashi, M., Raj, V., Youn, H.Y.
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
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Conference Proceeding
Generalized segmented channel routing
Shankar, V., Bhatia, D.
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
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Conference Proceeding
Floorplan area optimization using genetic algorithms
Rebaudengo, M., Sonza Reorda, M.
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
Published in Great Lakes 4th Symposium on VLSI: Design Automation of High Performance VLSI Systems (1994)
Get full text
Conference Proceeding