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A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS
Mangilal, Kunal Jain, Yilmaz, Mahmut, Agarwal, Vishal, Sarangi, Shantanu, Narayanun, Kaushik
Published in Proceedings - International Test Conference (03.11.2024)
Published in Proceedings - International Test Conference (03.11.2024)
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Conference Proceeding
A Lightweight Scan Architecture against the Scan-based Side-channel Attack
Wang, Xiangqi, Gong, Xingxing, Pan, Xianmin, Wang, Weizheng
Published in Journal of semiconductor technology and science (01.08.2023)
Published in Journal of semiconductor technology and science (01.08.2023)
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Journal Article
A secure scan architecture using parallel latch-based lock
Wang, Weizheng, Liang, Jian, Wang, Xiangqi, Pan, Xianmin, Cai, Shuo
Published in Integration (Amsterdam) (01.11.2023)
Published in Integration (Amsterdam) (01.11.2023)
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Journal Article
An efficient unused integrated circuits detection algorithm for parallel scan architecture
Sathyanarayana, Rekha, Kanathur Ramaswamy, Nataraj, Srikantaswamy, Mallikarjunaswamy, Kanathur Ramaswamy, Rekha
Published in International journal of electrical and computer engineering (Malacca, Malacca) (01.02.2024)
Published in International journal of electrical and computer engineering (Malacca, Malacca) (01.02.2024)
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Journal Article
A unified test data volume compression scheme for circular scan architecture using hosted cuckoo optimization
Shukla, Neeraj Kumar, Mayet, Abdulilah M., Raja, M. Ramkumar, Parayangat, Muneer, Usman, Mohammed, Verma, Rajesh, Bhutto, Javed Khan
Published in The Journal of supercomputing (01.03.2024)
Published in The Journal of supercomputing (01.03.2024)
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Journal Article
SSA: An Effective Secure Scan Architecture Based on Hidden, Randomly Inserted Keys and PUF
Wang, Weizheng, Wu, Zhizhi, Chen, Jinhai, Liu, Peng, Cai, Shuo, Xiong, Neal N.
Published in IEEE internet of things journal (15.07.2025)
Published in IEEE internet of things journal (15.07.2025)
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Journal Article
A Dynamic-Key Based Secure Scan Architecture for Manufacturing and In-Field IC Testing
Lee, Kuen-Jong, Liu, Ching-An, Wu, Chia-Chi
Published in IEEE transactions on emerging topics in computing (01.01.2022)
Published in IEEE transactions on emerging topics in computing (01.01.2022)
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Journal Article
Frequency scaled segmented (FSS) scan architecture for optimized scan-shift power and faster test application time
Pradeep, W., Narayanan, P., Mittal, R., Maheshwari, N., Naresh, N.
Published in Proceedings - International Test Conference (01.10.2017)
Published in Proceedings - International Test Conference (01.10.2017)
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Conference Proceeding
Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCs
Iwata, Hiroyuki, AbdAlwahab, Mahmoud, Press, Ron, Sugiura, Ohki
Published in Proceedings - International Test Conference (03.11.2024)
Published in Proceedings - International Test Conference (03.11.2024)
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Conference Proceeding