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Automating the pipeline of arithmetic datapaths
Istoan, Matei, de Dinechin, Florent
Published in Proceedings - Design, Automation, and Test in Europe Conference and Exhibition (01.03.2017)
Published in Proceedings - Design, Automation, and Test in Europe Conference and Exhibition (01.03.2017)
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Conference Proceeding
Hybrid analytical model of switched reluctance machine for real-time hardware-in-the-loop simulation
Xu, Fengqiu, Dinavahi, Venkata, Xu, Xianze
Published in IET electric power applications (01.07.2017)
Published in IET electric power applications (01.07.2017)
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Journal Article
High-efficiency pipeline design of binary arithmetic encoder
Song, Rui, Cui, HongFei, Li, YunSong, Wu, ChengKe
Published in Science China. Information sciences (01.09.2014)
Published in Science China. Information sciences (01.09.2014)
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Journal Article
Timing error detection and correction for power efficiency: an aggressive scaling approach
Rathnala, Prasanthi, Wilmshurst, Tim, Kharaz, Ahmad
Published in IET circuits, devices & systems (01.11.2018)
Published in IET circuits, devices & systems (01.11.2018)
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Journal Article