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Excellent Mechanical Durability of In‐Folding Stress of Poly‐Si Thin‐Film Transistor on Plastic Substrate Compared with Out‐Folding: Generation of Gate Leakage Currents in Flexible Poly‐Si Thin‐Film Transistor by Out‐Folding and Bias‐Temperature Stress
Kim, Dongjin, Billah, Mohammad Masum, Lee, Suhui, Siddik, Abu Bakar, Cho, Young Joo, Jang, Jin, Lee, Jaeseob, Lee, Yongsu, Shin, Jiyeong
Published in Advanced engineering materials (01.03.2021)
Published in Advanced engineering materials (01.03.2021)
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Journal Article
Exploiting Transistor Folding Layout as RHBD Technique Against Single-Event Transients
Aguiar, Y. Q., Wrobel, F., Autran, J.-L., Kastensmidt, F. L., Leroux, P., Saigne, F., Pouget, V., Touboul, A. D.
Published in IEEE transactions on nuclear science (01.07.2020)
Published in IEEE transactions on nuclear science (01.07.2020)
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Journal Article
Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis
Baek, Kyeonghyeon, Kim, Taewhan
Published in Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design (01.11.2021)
Published in Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design (01.11.2021)
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Conference Proceeding
Area-Optimal Transistor Folding for 1-D Gridded Cell Design
Cortadella, Jordi
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2013)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2013)
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Journal Article
Publication
Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding
Smaniotto, Gustavo H., Moreira, Matheus T., Ziesemer, Adriel M., Marques, Felipe S., da Rosa, Leomar S.
Published in Conference proceedings : Midwest Symposium on Circuits and Systems (01.10.2016)
Published in Conference proceedings : Midwest Symposium on Circuits and Systems (01.10.2016)
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Conference Proceeding
An Efficient Transistor Folding Algorithm For Row-based Cmos Layout Design
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Conference Proceeding
Application of a Quantum-Well Silicon NMOS Transistor as a Folding Amplifier Frequency Multiplier
Naquin, Clint, Yongda Cai, Gangyi Hu, Lee, Mark, Yun Chiu, Edwards, Hal, Mathur, Guru, Chatterjee, Tathagata, Maggio, Ken
Published in IEEE journal of the Electron Devices Society (01.05.2017)
Published in IEEE journal of the Electron Devices Society (01.05.2017)
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Journal Article
Simultaneous transistor pairing and placement for CMOS standard cells
Ang Lu, Hsueh-Ju Lu, En-Jang Jang, Yu-Po Lin, Chun-Hsiang Hung, Chun-Chih Chuang, Rung-Bin Lin
Published in 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01.03.2015)
Published in 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01.03.2015)
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Conference Proceeding
Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool
Smaniotto, Gustavo H., Machado, Joao J. S., Moreira, Matheus T., Ziesemer, Adriel M., Marques, Felipe S., da Rosa, Leomar S.
Published in 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS) (11.04.2016)
Published in 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS) (11.04.2016)
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Conference Proceeding
Pull up transistor folding
Li, W.-N., Sahni, S.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.05.1990)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.05.1990)
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Journal Article
A technique for pull-up transistor folding
Lursinsap, C., Gajski, D.D.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.08.1988)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.08.1988)
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Journal Article