HDL with digital design : VHDL and Verilog

This book introduces the latest version of hardware description languages and explains how the languages can be implemented in the design of the digital logic components. In addition to digital design, other examples in the areas of bioengineering and basic computer design are covered. It introduces...

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Bibliographic Details
Main Author Botros, Nazeih, 1945- (Author)
Format Electronic eBook
LanguageEnglish
Published Dulles, Virginia : Mercury Learning and Information, [2015]
SeriesEngineering series.
Subjects
Computer hardware description languages.
VHDL (Computer hardware description language)
Verilog (Computer hardware description language)
Integrated circuits > Design and construction > Data processing.
elektronické knihy
electronic books
Online AccessFull text
ISBN9781942270287
1942270283
9781523101344
1523101342
9781938549816
1938549813
1938549864
9781938549861
Physical Description1 online resource (xiv, 564 pages) : illustrations

Cover

Table of Contents:
  • Introduction
  • Hardware description languages
  • Structure of the HDL module
  • Structure of Verilog Module
  • Stles (types) of description
  • Data flow description
  • Behavioral description
  • Structural description
  • Switch-level description
  • Mixed-type description
  • Mixed-languages description
  • Ports
  • VHDL ports
  • Verilog ports
  • Operators
  • Logical operators
  • VHDL logical operators
  • Verilog logical operators
  • Relational Operators
  • VHD Relational Operators
  • Verilog Relational Operators
  • Arithmetic Operators
  • VHD Arithmeti Operators
  • Verilog Arithmeti Operators
  • Arithmetic operator precedence
  • Shift and rotate operators
  • VHDL shift/rotate operators
  • Verilog shift operators
  • Date types
  • VHDL Data types
  • Scalar types
  • Composite types
  • Access types
  • File types
  • Other types
  • Verilog data types
  • Nets
  • Register
  • Vectors
  • Integers
  • Real
  • Parameter
  • Arrays
  • Simulation and synthesis
  • Brief comparison of VHDL and verilog
  • Summary
  • Exercises
  • Chapter 2 Data-flow description
  • Highlights of data-flow description
  • Signal declaration and assignment statement
  • Constant declaration and constant assignment statements
  • Assigning a delay time to the signal-assignment
  • Data type: Vector
  • Common programming errors
  • Common VHDL programming errors vCommon verilog programming errors
  • Chapter 3 Behavioral description
  • Behavioral description highlights
  • Structure of the HDL behavioral description
  • The VHDL variable-assignment statement
  • Sequential statements
  • IF statement
  • Analysis of VHDL code in listings 3.2 and 3.3
  • Case statement
  • Verilog casex and casez
  • The wait-for statement
  • Loop statement
  • For-loop
  • While -loop
  • Verilog repeat
  • Verilog forever
  • VHDL next and exit Chapter 4 Structural description
  • Highlights of structural description
  • Organization of structural description
  • Binding
  • State machines
  • generate(HDL, generic (VHDL) and parameter (verilog)
  • Switch-level description
  • Highlights of switch-level description
  • Useful definitions
  • Single NMOS and PMOS switches
  • Verilog description of NMOS and PMOS switches
  • Verilog description of NMOS and PMOS switches
  • Procedure, tasks, and functions
  • MIxed-type description
  • Advanced HDL description
  • Synthesis basics.

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