rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: HDL with digital design
    sub title: VHDL and Verilog
  title info:
    title: Hardware description language with digital design
    sub title: Very High Speed Integrated Circuit Hardware Description Language and Verilog
  name:
    name part: Botros, Nazeih
    name part: 1945-
    role:
      role term: creator
    role:
      role term: author.
  type of resource: text
  genre: bibliography
  genre: elektronické knihy
  genre: electronic books
  origin info:
    place:
      place term: vau
    date issued: 2015
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: remote
    extent: 1 online resource (xiv, 564 pages) : illustrations
  abstract: This book introduces the latest version of hardware description languages and explains how the languages can be implemented in the design of the digital logic components. In addition to digital design, other examples in the areas of bioengineering and basic computer design are covered. It introduces mixed language programming by covering both Verilog and VHDL side by side. Students, as well as professionals, can learn both the theoretical and practical concepts of digital design. The two languages are equally important in the field of computer engineering and computer science as well as other engineering fields such as simulation and modeling. This resource uses the latest versions of both Verilog and VHDL; includes fundamentals of synthesis and FPGAs implementation; instructor's resources available upon adoption. --
  table of contents: Introduction -- Hardware description languages -- Structure of the HDL module -- Structure of Verilog Module -- Stles (types) of description -- Data flow description -- Behavioral description -- Structural description -- Switch-level description -- Mixed-type description -- Mixed-languages description -- Ports -- VHDL ports -- Verilog ports -- Operators -- Logical operators -- VHDL logical operators -- Verilog logical operators -- Relational Operators -- VHD Relational Operators -- Verilog Relational Operators -- Arithmetic Operators -- VHD Arithmeti Operators -- Verilog Arithmeti Operators -- Arithmetic operator precedence -- Shift and rotate operators -- VHDL shift/rotate operators -- Verilog shift operators -- Date types -- VHDL Data types -- Scalar types -- Composite types -- Access types -- File types -- Other types -- Verilog data types -- Nets -- Register -- Vectors -- Integers -- Real -- Parameter -- Arrays -- Simulation and synthesis -- Brief comparison of VHDL and verilog -- Summary -- Exercises -- Chapter 2 Data-flow description -- Highlights of data-flow description -- Signal declaration and assignment statement -- Constant declaration and constant assignment statements -- Assigning a delay time to the signal-assignment -- Data type: Vector -- Common programming errors -- Common VHDL programming errors vCommon verilog programming errors -- Chapter 3 Behavioral description -- Behavioral description highlights -- Structure of the HDL behavioral description -- The VHDL variable-assignment statement -- Sequential statements -- IF statement -- Analysis of VHDL code in listings 3.2 and 3.3 -- Case statement -- Verilog casex and casez -- The wait-for statement -- Loop statement -- For-loop -- While -loop -- Verilog repeat -- Verilog forever -- VHDL next and exit Chapter 4 Structural description -- Highlights of structural description -- Organization of structural description -- Binding -- State machines -- generate(HDL, generic (VHDL) and parameter (verilog) --…
  note: Nazeih Botros.
  note: Includes index.
  note: Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty
  note: Includes bibliographical references at the end of each chapters and index.
  subject:
    topic: Computer hardware description languages
  subject:
    topic: VHDL (Computer hardware description language)
  subject:
    topic: Verilog (Computer hardware description language)
  subject:
    topic: Integrated circuits
    topic: Design and construction
    topic: Data processing
  related item:
    title info:
      title: HDL with digital design
    name:
      name part: Botros, Nazeih, 1945-
    origin info:
      publisher: Dulles, Virginia : Mercury Learning and Information, [2015]
    identifier: (OCoLC)908628126
  related item:
    title info:
      title: Engineering series
  identifier: 9781942270287
  identifier: 1942270283
  identifier: 9781523101344
  identifier: 1523101342
  identifier: 9781938549816
  identifier: 1938549813
  identifier: 1938549864
  identifier: 9781938549861
  identifier: https://proxy.k.utb.cz/login
  access condition: Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty
  record info:
    record content source: LGG
    record creation date: 150603
    record change date: 20240717213016.0
    record identifier: kn-ocn910636111
    language of cataloging:
      language term: eng