Computer architecture : a quantitative approach

• Main Authors: Hennessy, John L., (Author), Patterson, David A., (Author)
• Other Authors: Asanović, Krste, (Contributor)
• Format: eBook
• Language: English
• Published: Amsterdam ; Boston : Morgan Kaufmann/Elsevier, ©2012.
• Edition: Fifth edition.
• Series: The Morgan Kaufmann series in computer architecture and design
• Subjects: Computer architecture.; elektronické knihy; electronic books
• ISBN: 9780123838735; 0123838738; 9780123838728; 012383872X; 6613298972; 9786613298973; 0128119063; 9780128119068; 128329897X; 9781283298971
• Physical Description: 1 online resource (xxviii, 493, [325] pages) : illustrations
• Access: Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty

'Computer Architecture: A Quantitative Approach', Fifth Edition, explores the ways that software and technology in the cloud are accessed by digital media, such as cell phones, computers, tablets, and other mobile devices. The book became a part of Intel's 2012 recommended reading list for developers, and it covers the revolution of mobile computing. The text also highlights the two most important factors in architecture today : parallelism and memory hierarchy. The six chapters that this book is composed of follow a consistent framework : explanation of the ideas in each chapter ; a "crosscutting issues" section, which presents how the concepts covered in one chapter connect with those given in other chapters ; a "putting it all together" section that links these concepts by discussing how they are applied in real machine ; and detailed examples of misunderstandings and architectural traps commonly encountered by developers and architects. The first chapter of the book includes formulas for energy, static and dynamic power, integrated circuit costs, reliability, and availability. Chapter 2 discusses memory hierarchy and includes discussions about virtual machines, SRAM and DRAM technologies, and new material on Flash memory. The third chapter covers the exploitation of instruction-level parallelism in high-performance processors, superscalar execution, dynamic scheduling and multithreading, followed by an introduction to vector architectures in the fourth chapter. Chapters 5 and 6 describe multicore processors and warehouse-scale computers (WSCs), respectively.