Design and test technology for dependable systems-on-chip

"This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"--

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Bibliographic Details
Other Authors: Ubar, Raimund, 1941-, Raik, Jaan, 1972-, Vierhaus, Heinrich Theodor, 1951-
Format: eBook
Language: English
Published: Hershey, PA : Information Science Reference, ©2010.
Subjects:
Systems on a chip > Design and construction.
Networks on a chip > Design and construction.
Systems on a chip > Testing.
Networks on a chip > Testing.
elektronické knihy
electronic books
ISBN: 9781609602123
1609602129
9781609602147
1609602145
9781621989547
1621989542
1283019736
9781283019736
9786613019738
6613019739
Physical Description: 1 online resource (xxvi, 550 pages) : illustrations

Cover

Table of contents

LEADER 03153cam a2200505 a 4500
001 kn-ocn713272704
003 OCoLC
005 20240717213016.0
006 m o d
007 cr cn|||||||||
008 110419s2010 paua ob 001 0 eng d
040 |a N$T  |b eng  |e pn  |c N$T  |d E7B  |d OTZ  |d OCLCQ  |d CDX  |d OCLCQ  |d KNOVL  |d ZCU  |d KNOVL  |d OCLCQ  |d VT2  |d REB  |d OCLCF  |d CEF  |d RRP  |d OCLCQ  |d HS0  |d OCLCQ  |d OCLCO  |d OCLCQ  |d OCLCO  |d OCLCL  |d SXB 
020 |a 9781609602123  |q (electronic bk.) 
020 |a 1609602129  |q (electronic bk.) 
020 |a 9781609602147  |q (electronic bk.) 
020 |a 1609602145  |q (electronic bk.) 
020 |a 9781621989547  |q (electronic bk.) 
020 |a 1621989542  |q (electronic bk.) 
020 |a 1283019736 
020 |a 9781283019736 
020 |a 9786613019738 
020 |a 6613019739 
035 |a (OCoLC)713272704  |z (OCoLC)961846013  |z (OCoLC)995021281  |z (OCoLC)1026430349  |z (OCoLC)1062935932  |z (OCoLC)1087430768  |z (OCoLC)1109244125  |z (OCoLC)1136265564 
245 0 0 |a Design and test technology for dependable systems-on-chip /  |c Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors. 
260 |a Hershey, PA :  |b Information Science Reference,  |c ©2010. 
300 |a 1 online resource (xxvi, 550 pages) :  |b illustrations 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
504 |a Includes bibliographical references and index. 
506 |a Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty 
520 |a "This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"--  |c Provided by publisher 
505 0 |a Section 1. Design, modeling, and verification -- section 2. Faults, compensation and repair -- section 3. Fault simulation and fault injection -- section 4. Test technology for systems-on-chip -- section 5. Test planning, compression and compaction in SoC's. 
590 |a Knovel  |b Knovel (All titles) 
650 0 |a Systems on a chip  |x Design and construction. 
650 0 |a Networks on a chip  |x Design and construction. 
650 0 |a Systems on a chip  |x Testing. 
650 0 |a Networks on a chip  |x Testing. 
655 7 |a elektronické knihy  |7 fd186907  |2 czenas 
655 9 |a electronic books  |2 eczenas 
700 1 |a Ubar, Raimund,  |d 1941-  |1 https://id.oclc.org/worldcat/entity/E39PBJtCBDmXB8d8bFvHVvGbVC 
700 1 |a Raik, Jaan,  |d 1972-  |1 https://id.oclc.org/worldcat/entity/E39PBJt43fwDhVqYRdt3rqBMfq 
700 1 |a Vierhaus, Heinrich Theodor,  |d 1951-  |1 https://id.oclc.org/worldcat/entity/E39PCjKh7DVpFyFKrKwRHC8w83 
776 0 8 |i Print version:  |t Design and test technology for dependable systems-on-chip.  |d Hershey, PA : Information Science Reference, ©2010  |z 9781609602123  |w (DLC) 2010045850  |w (OCoLC)617382265 
856 4 0 |u https://proxy.k.utb.cz/login?url=https://app.knovel.com/hotlink/toc/id:kpDTTDSC01/design-and-test?kpromoter=marc  |y Full text 

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