Nanoscale MOS transistors : semi-classical transport and applications

"Written from an engineering standpoint, this book provides the theoretical background and physical insight needed to understand new and future developments in the modeling and design of n- and p-MOS nanoscale transistors. A wealth of applications, illustrations and examples connect the methods...

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Bibliographic Details
Main Author: Esseni, D.
Other Authors: Palestri, P., Selmi, L.
Format: eBook
Language: English
Published: Cambridge ; New York : Cambridge University Press, 2011.
Subjects:
Metal oxide semiconductors > Design and construction.
Electron transport.
Nanoelectronics.
elektronické knihy
electronic books
ISBN: 9780511930522
0511930526
9780511933226
0511933223
9780511923753
0511923759
9780511973857
0511973853
9780511928017
0511928017
9780521516846
0521516846
Physical Description: 1 online resource (xvii, 470 pages) : illustrations

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Table of contents

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100 1 |a Esseni, D.  |q (David) 
245 1 0 |a Nanoscale MOS transistors :  |b semi-classical transport and applications /  |c David Esseni, Pierpaolo Palestri, and Luca Selmi. 
260 |a Cambridge ;  |a New York :  |b Cambridge University Press,  |c 2011. 
300 |a 1 online resource (xvii, 470 pages) :  |b illustrations 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
504 |a Includes bibliographical references and index. 
506 |a Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty 
520 |a "Written from an engineering standpoint, this book provides the theoretical background and physical insight needed to understand new and future developments in the modeling and design of n- and p-MOS nanoscale transistors. A wealth of applications, illustrations and examples connect the methods described to all the latest issues in nanoscale MOSFET design. Key areas covered include: Transport in arbitrary crystal orientations and strain conditions, and new channel and gate stack materials All the relevant transport regimes, ranging from low field mobility to quasi-ballistic transport, described using a single modeling framework Predictive capabilities of device models, discussed with systematic comparisons to experimental results"--  |c Provided by publisher. 
520 |a "The traditional geometrical scaling of the CMOS technologies has recently evolved in a generalized scaling scenario where material innovations for different intrinsic regions of MOS transistors as well as new device architectures are considered as the main routes toward further performance improvements. In this regard, high-? dielectrics are used to reduce the gate leakage with respect to the SiO2 for a given drive capacitance, while the on-current of the MOS transistors is improved by using strained silicon and possibly with the introduction of alternative channel materials. Moreover, the ultra-thin body Silicon-On-Insulator (SOI) device architecture shows an excellent scalability even with a very lightly doped silicon film, while non-planar FinFETs are also of particular interest, because they are a viable way to obtain double-gate SOI MOSFETs and to realize in the same fabrication process n-MOS and p-MOS devices with different crystal orientations"--  |c Provided by publisher. 
505 0 |a 1. Introduction; 2. Bulk semiconductors and the semi-classical model; 3. Quantum confined inversion layers; 4. Carrier scattering in silicon MOS transistors; 5. The Boltzmann transport equation; 6. The Monte Carlo method for the Boltzmann transport equation; 7. Simulation of bulk and SOI silicon MOSFETs; 8. MOS transistors with arbitrary crystal orientation; 9. MOS transistors with strained silicon channels; 10. MOS transistors with alternative materials; Appendix A. Mathematical definitions and properties; Appendix B. Integrals and transformations over a finite area A; Appendix C. Calculation of the equi-energy lines with the k-p model; Appendix D. Matrix elements beyond the envelope function approximation; Appendix E. Charge density produced by a perturbation potential. 
590 |a Knovel  |b Knovel (All titles) 
650 0 |a Metal oxide semiconductors  |x Design and construction. 
650 0 |a Electron transport. 
650 0 |a Nanoelectronics. 
655 7 |a elektronické knihy  |7 fd186907  |2 czenas 
655 9 |a electronic books  |2 eczenas 
700 1 |a Palestri, P.  |q (Pierpaolo) 
700 1 |a Selmi, L.  |q (Luca) 
776 0 8 |i Print version:  |a Esseni, D. (David).  |t Nanoscale MOS transistors.  |d Cambridge ; New York : Cambridge University Press, 2011  |z 9780521516846  |w (DLC) 2010046886  |w (OCoLC)651920159 
856 4 0 |u https://proxy.k.utb.cz/login?url=https://app.knovel.com/hotlink/toc/id:kpNMOSTSC5/nanoscale-mos-transistors?kpromoter=marc  |y Full text 

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