System-on-chip test architectures : nanometer design for testability

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semic...

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Bibliographic Details
Other Authors Wang, Laung-Terng, Stroud, Charles E., Touba, Nur A.
Format Electronic eBook
LanguageEnglish
Published Amsterdam ; Boston : Morgan Kaufmann Publishers, ©2008.
SeriesMorgan Kaufmann series in systems on silicon.
Subjects
Systems on a chip > Testing.
Integrated circuits > Very large scale integration > Testing.
Integrated circuits > Very large scale integration > Design.
elektronické knihy
electronic books
Online AccessFull text
ISBN9780123739735
012373973X
9780080556802
0080556809
1281100048
9781281100047
9786611100049
6611100040
Physical Description1 online resource (xxxvi, 856 pages) : illustrations

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Table of Contents:
  • Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.

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