rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: System-on-chip test architectures
    sub title: nanometer design for testability
  name:
    name part: Wang, Laung-Terng.
  name:
    name part: Stroud, Charles E.
  name:
    name part: Touba, Nur A.
  type of resource: text
  genre: bibliography
  genre: elektronické knihy
  genre: electronic books
  origin info:
    place:
      place term: ne
    place:
      place term: Amsterdam
    place:
      place term: Boston
    publisher: Morgan Kaufmann Publishers
    date issued: ©2008
    date issued: 2008
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: remote
    extent: 1 online resource (xxxvi, 856 pages) : illustrations
  abstract: Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students.
  table of contents: Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.
  note: edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba.
  note: Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty
  note: Includes bibliographical references and index.
  subject:
    topic: Systems on a chip
    topic: Testing
  subject:
    topic: Integrated circuits
    topic: Very large scale integration
    topic: Testing
  subject:
    topic: Integrated circuits
    topic: Very large scale integration
    topic: Design
  related item:
    title info:
      title: System-on-chip test architectures
    origin info:
      publisher: Amsterdam ; Boston : Morgan Kaufmann Publishers, ©2008
    identifier: (DLC) 2007023373
    identifier: (OCoLC)140109577
  related item:
    title info:
      title: Morgan Kaufmann series in systems on silicon
  identifier: 9780123739735
  identifier: 012373973X
  identifier: 9780080556802
  identifier: 0080556809
  identifier: 1281100048
  identifier: 9781281100047
  identifier: 9786611100049
  identifier: 6611100040
  identifier: https://proxy.k.utb.cz/login
  access condition: Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty
  record info:
    record content source: OPELS
    record creation date: 080516
    record change date: 20240717213016.0
    record identifier: kn-ocn228148482
    language of cataloging:
      language term: eng