Memory systems : cache, DRAM, disk
Is your memory hierarchy stopping your microprocessor from performing at the high level it should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem. The book tells you everything you need to know about the logical design and operation, physical design and operation, perform...
Saved in:
Main Author: | |
---|---|
Other Authors: | , |
Format: | eBook |
Language: | English |
Published: |
Burlington, MA :
Morgan Kaufmann Publishers,
©2008.
|
Subjects: | |
ISBN: | 9780123797513 0123797519 9780080553849 0080553842 9786611766450 6611766456 1322465541 9781322465548 1281766453 9781281766458 |
Physical Description: | 1 online resource (xxxiv, 982 pages) : illustrations |
LEADER | 04535cam a2200469 a 4500 | ||
---|---|---|---|
001 | kn-ocn228148220 | ||
003 | OCoLC | ||
005 | 20240717213016.0 | ||
006 | m o d | ||
007 | cr cn||||||||| | ||
008 | 080516s2008 maua ob 001 0 eng d | ||
040 | |a OPELS |b eng |e pn |c OPELS |d OCLCQ |d QE2 |d N$T |d IDEBK |d E7B |d B24X7 |d DKDLA |d KNOVL |d OCLCQ |d KNOVL |d OCLCF |d OCLCQ |d KNOVL |d YDXCP |d OCLCQ |d AZK |d COCUF |d AGLDB |d STF |d MOR |d PIFAG |d OCLCQ |d NJR |d U3W |d OCLCQ |d WRM |d D6H |d VTS |d INT |d NRAMU |d VT2 |d OCLCQ |d COO |d WYU |d JBG |d OCLCQ |d LEAUB |d M8D |d OCLCQ |d NLW |d K6U |d VLY |d UKCRE |d OCLCQ |d OCLCO |d MHW |d OCLCO |d OCLCQ |d OCLCO |d OCLCL |d EZC | ||
020 | |a 9780123797513 | ||
020 | |a 0123797519 | ||
020 | |a 9780080553849 |q (electronic bk.) | ||
020 | |a 0080553842 |q (electronic bk.) | ||
020 | |a 9786611766450 | ||
020 | |a 6611766456 | ||
020 | |a 1322465541 | ||
020 | |a 9781322465548 | ||
020 | |a 1281766453 | ||
020 | |a 9781281766458 | ||
035 | |a (OCoLC)228148220 |z (OCoLC)299769008 |z (OCoLC)471135855 |z (OCoLC)473205215 |z (OCoLC)647888043 |z (OCoLC)771939208 |z (OCoLC)961505925 |z (OCoLC)962723003 |z (OCoLC)984814799 |z (OCoLC)988530780 |z (OCoLC)992051462 |z (OCoLC)1034920248 |z (OCoLC)1037943003 |z (OCoLC)1038648858 |z (OCoLC)1045530156 |z (OCoLC)1062874131 |z (OCoLC)1081294276 |z (OCoLC)1103268555 |z (OCoLC)1118369264 |z (OCoLC)1129335380 |z (OCoLC)1153022156 |z (OCoLC)1162205073 |z (OCoLC)1192329677 |z (OCoLC)1228609122 |z (OCoLC)1240509269 | ||
100 | 1 | |a Jacob, Bruce. | |
245 | 1 | 0 | |a Memory systems : |b cache, DRAM, disk / |c Bruce Jacob, Spencer W. Ng, David T. Wang ; with contributions by Samuel Rodriguez. |
260 | |a Burlington, MA : |b Morgan Kaufmann Publishers, |c ©2008. | ||
300 | |a 1 online resource (xxxiv, 982 pages) : |b illustrations | ||
336 | |a text |b txt |2 rdacontent | ||
337 | |a computer |b c |2 rdamedia | ||
338 | |a online resource |b cr |2 rdacarrier | ||
506 | |a Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty | ||
520 | |a Is your memory hierarchy stopping your microprocessor from performing at the high level it should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem. The book tells you everything you need to know about the logical design and operation, physical design and operation, performance characteristics and resulting design trade-offs, and the energy consumption of modern memory hierarchies. You learn how to to tackle the challenging optimization problems that result from the side-effects that can appear at any point in the entire hierarchy. As a result you will be able to design and emulate the entire memory hierarchy. Understand all levels of the system hierarchy -Xcache, DRAM, and disk. Evaluate the system-level effects of all design choices. Model performance and energy consumption for each component in the memory hierarchy. | ||
505 | 0 | |a Overview: On the Topic of Memory Systems and Their Design Part I: Cache Ch. 1. An Overview of Cache Principles 2. Logical Organization 3. Management of Cache Contents 4. Cache Cohenrence 5. Implementation Issues 6. Cache Case Studies Part II: DRAM 7. Memory Systems Overview 8. DRAM Device: Basic Circuits and Architecture 9. DRAM System Signalling and Timing 10. DRAM Memory System Organization 11. Generic DRAM Memory Access Protocol 12. Evolution of DRAM Devices 13. DRAM Memory Controller 14. Memory System Design Analysis Part II: Disk 15. Overview of Disks 16. The Physical Layer 17. The Data Layer 18. Performance Issues and Design Tradeoffs 19. Drive Interface 20. Operational Performance Improvement 21. The Cache Layer, 23. Performance Testing 24. Storage Subsystems 25. Advanced Topics 26. Case Study Part IV: Cross-Cutting Issues 27. The Holistic Design of Memory Hierarchies 28. Analysis of Cost and Performance 29. Power and Energy 30. Reliability 31. Virtual Memory. | |
504 | |a Includes bibliographical references and index. | ||
590 | |a Knovel |b Knovel (All titles) | ||
650 | 0 | |a Computer storage devices. | |
655 | 7 | |a elektronické knihy |7 fd186907 |2 czenas | |
655 | 9 | |a electronic books |2 eczenas | |
700 | 1 | |a Ng, Spencer W. | |
700 | 1 | |a Wang, David T., |d 1968- |1 https://id.oclc.org/worldcat/entity/E39PCjGyFgg6mygHywYMTWvXQy | |
776 | 0 | 8 | |i Print version: |a Jacob, Bruce. |t Memory systems. |d Burlington, MA : Morgan Kaufmann Publishers, ©2008 |z 9780123797513 |z 0123797519 |w (DLC) 2007282120 |w (OCoLC)183179641 |
856 | 4 | 0 | |u https://proxy.k.utb.cz/login?url=https://app.knovel.com/hotlink/toc/id:kpMSCDRAM1/memory-systems-cache?kpromoter=marc |y Full text |