Non-logic devices in logic processes

• Main Authors: Ma, Yanjun (Author), Kan, Edwin (Author)
• Format: Electronic eBook
• Language: English
• Published: Cham, Switzerland : Springer, [2017]
• Subjects: Metal oxide semiconductors, Complementary.; elektronické knihy; electronic books
• ISBN: 9783319483399; 9783319483375
• Physical Description: 1 online resource (xxii, 284 pages) : color illustrations

This book shows readers how to design semiconductor devices using the most common and lowest cost logic CMOS processes. Readers will benefit from the author's extensive, industrial experience and the practical approach he describes for designing efficiently semiconductor devices that typically...

Table of Contents:

• Preface; Organization of This Book; Acknowledgements; Contents; Abbreviations; About the Authors; Part I: Basics; Chapter 1: Introduction; 1.1 The Semiconductor Industry; 1.2 Mooreś Law and Its Corollaries; 1.3 Aim and Scope of This Book; References; Chapter 2: Overview of Logic CMOS Devices; 2.1 Basic CMOS Devices and Processes; 2.1.1 Diodes; 2.1.2 Capacitors; 2.1.3 Resistors; 2.1.4 Bipolar Transistors; 2.1.5 MOSFETs; 2.2 Physics of Diodes; 2.2.1 The p-n JunctionDiode; 2.2.2 Current-Voltage Characteristics; 2.2.3 Junction Breakdowns; 2.2.4 Schottky Diodes.
• 2.3 MOS Capacitors and Oxide Device Physics2.3.1 MOS Capacitors; 2.3.2 Gate Tunneling Current; 2.3.3 Oxide Reliability; 2.4 MOSFET Physics; 2.4.1 Basic Long-Channel MOSFET Equations; 2.4.2 Capacitances of MOSFET; 2.4.3 Nonideal Effects; 2.4.4 Hot Carrier Reliability of MOSFET; 2.5 CMOS Circuits and Power Consumption; 2.6 Non-logic CMOS Devices Discussed in This Book; References; Chapter 3: Overview of Logic CMOS Processes; 3.1 Generic Logic CMOS Processes; 3.1.1 Introduction; 3.1.2 Process Flow and Mask Design; 3.2 Layout and Mask Generation; 3.3 Design Rules.
• 3.4 Extension of Logic CMOS Processes3.5 Process Control; 3.6 Postprocessing; 3.6.1 Dicing; 3.6.2 3D IC Integration and Through Silicon Via; 3.7 Wafer Processing Economics; 3.7.1 Wafer Processing Cost; 3.7.2 Yield; 3.7.3 Cost of Chips; References; Part II: Non-logic Device Design in Logic Processes; Chapter 4: Non-logic MOSFETs in Logic CMOS Processes; 4.1 Introduction; 4.2 MOSFETs with Nonstandard Threshold Voltages; 4.2.1 Bandgap-Engineered MOSFETs; 4.2.2 Bandgap FET Application: Voltage Reference Circuit; 4.2.3 Source-Drain-Engineered MOSFET; 4.3 High-Voltage MOSFET; 4.3.1 Introduction.
• 4.3.2 LDMOS4.3.3 Improving High-Voltage Performance; 4.3.4 Manufacturing Challenges; References; Chapter 5: Floating-Gate Devices in Logic CMOS Processes; 5.1 Introduction; 5.2 Floating-Gate Transistors; 5.3 Floating-Gate Capacitor; 5.4 Semifloating Embedded DRAM Cell; 5.5 Concluding Remarks; References; Chapter 6: Bipolar Transistors in Logic CMOS Processes; 6.1 Introduction; 6.2 Parasitic Bipolar Transistors; 6.3 Reference Circuits Using Parasitic BJTs; 6.4 Punchthrough Transistor; References; Chapter 7: Diodes in Logic CMOS Processes; 7.1 Introduction; 7.2 Polysilicon Diodes.
• 7.2.1 Polysilicon Resistors7.3 Schottky Diodes; References; Part III: Selected Applications; Chapter 8: Logic Nonvolatile Memory; 8.1 Introduction to Embedded NVM; 8.2 Logic NVM; 8.3 Programming and Erase Methods; 8.4 Memory Cell Design Considerations; 8.5 Memory Arrays; 8.5.1 High-Voltage Generators; 8.5.2 Row and Column Decoders; 8.5.3 Sense Amplifiers; 8.6 Memory Reliability; 8.6.1 Data Retention; 8.6.2 Program/Erase Endurance; 8.6.3 Disturb; 8.6.4 Improving Data Retention Reliability; 8.7 An Application of LNVM; References; Chapter 9: One-Time Programmable Memories in Logic Processes.