Materials for advanced packaging

This book provides a comprehensive overview of the recent developments in advanced packaging. Established techniques are discussed, as well as emerging technologies, in order to provide readers with the most up-to-date developments.

Saved in:
Bibliographic Details
Other Authors Lu, Daniel, Wong, C. P.
Format Electronic eBook
LanguageEnglish
Published Cham : Springer, [2016], ©2017.
Edition2nd ed.
Subjects
Online AccessFull text
ISBN9783319450988
9783319450971
Physical Description1 online resource (974 pages)

Cover

LEADER 00000cam a2200000Mi 4500
001 99583
003 CZ-ZlUTB
005 20251008111954.0
006 m o d
007 cr |n|---|||||
008 161126t20162017sz o 000 0 eng d
040 |a EBLCP  |b eng  |e pn  |c EBLCP  |d YDX  |d OCLCQ  |d GW5XE  |d OCLCF  |d UAB  |d IOG  |d ESU  |d JBG  |d IAD  |d ICW  |d ICN  |d OTZ  |d U3W  |d CAUOI  |d OCLCQ  |d KSU  |d OCLCQ 
020 |a 9783319450988  |q (electronic bk.) 
020 |z 9783319450971 
035 |a (OCoLC)964403453  |z (OCoLC)964336205 
245 0 0 |a Materials for advanced packaging /  |c Daniel Lu, C.P. Wong, editors. 
250 |a 2nd ed. 
260 |a Cham :  |b Springer,  |c [2016], ©2017. 
300 |a 1 online resource (974 pages) 
336 |a text  |b txt  |2 rdacontent 
337 |a počítač  |b c  |2 rdamedia 
338 |a online zdroj  |b cr  |2 rdacarrier 
505 0 |a Preface; Preface to the First Edition; Contents; Contributors; About the Authors; Chapter 1: 3D Integration Technologies: An Overview; 1.1 Introduction; 1.1.1 Motivation for 3D Integration; 1.1.2 Technology Platforms for 3D Integration and Packaging; 1.2 Major Key Enabling 3D Technologies and Materials; 1.2.1 Typical 3D Integration Process Flows; 1.2.2 Wafer Thinning and Dicing; 1.2.3 Wafer and Chip Stacking; 1.3 TSV Integration Scheme and Process; 1.3.1 TSV Integration Scheme and Process; 1.3.1.1 TSV Integration Scheme; 1.3.1.2 TSV Process Flow; 1.3.1.3 TSV Scaling. 
505 8 |a 1.3.2 Alternative TSV Process Options1.4 Potential Limitations to 3D System Integration; 1.5 Major Applications of 3D Integration; 1.6 3D Integration Perspectives; References; Chapter 2: Advanced Bonding/Joining Techniques; 2.1 Adhesive Bonding Techniques; 2.1.1 Adhesives in the Electronic Industries; 2.1.1.1 Epoxy Resins; 2.1.1.2 Silicone Resins; 2.1.1.3 Polyimides; 2.1.1.4 Acrylics; 2.1.2 Applications of Adhesives in Electronics; 2.1.2.1 Integrated Circuits; 2.1.2.2 Flexible Circuit; 2.1.2.3 Liquid Crystal Display; 2.1.3 New Adhesives; 2.1.3.1 Liquid Crystal Polymer (LCP). 
505 8 |a 2.1.3.2 SU 8 Adhesive Bonding2.2 Lead-Free Soldering Processes; 2.2.1 Basic Soldering Processes; 2.2.2 The Fluxless Processes Dealing with Tin Oxides; 2.2.3 Oxidation-Free Fluxless Soldering Technology; 2.3 Bonding Processes Using Silver Indium System for High Temperature Applications; 2.3.1 Silver-Indium Phase Diagram and Reactions at 180C; 2.3.2 Si Chips Bonded to Ag/Cu Substrates Using Ag-In System; 2.3.3 Bonding Silicon Chips to Aluminum Substrates Using Ag-In System Without Flux; 2.3.4 The Strength of High Temperature Ag-In Joints Made Between Copper by Fluxless Low Temperature Processes. 
505 8 |a 2.3.5 Thermal Cycling Reliability Study of Ag-In Joints Between Si Chips and Cu Substrates Made by Fluxless Processes2.4 Solid-State Bonding Technology; 2.4.1 Introduction to Solid-State Bonding; 2.4.2 Fundamental Principle of Solid-State Bonding; 2.4.3 The Quantum Solid-State Bonding Theory; 2.4.4 Novel Ag-to-Cu Solid-State Bonding a.k.a Direct Bonding; 2.4.5 Cu-to-Ag/Cu Solid-State Bonding; 2.5 Silver Flip-Chip Interconnect Technology; 2.5.1 10mum Silver Flip-Chip Joints Made by 250C Solid-State Bonding Process; References; Chapter 3: Advanced Chip-to-Substrate Connections; 3.1 Introduction. 
505 8 |a 3.1.1 ITRS Projections for Flip-Chip Connections3.1.2 Electrical Modeling of I/O; 3.1.2.1 Parasitic Inductance of Chip-to-Substrate I/O; 3.1.2.2 Parasitic I/O Capacitance; 3.1.2.3 Characteristic Impedance; 3.1.3 Mechanical Modeling; 3.2 Compliant Solder-Based I/O Structures; 3.2.1 Peripheral-to-Flip-Chip Area Array Structures; 3.2.2 Redistribution Using Area Array Solder I/O; 3.3 Wafer-Scale Compliant I/O; 3.4 Improved Mechanical Performance Solder-Capped Structures; 3.5 Solder-Free Chip-to-Substrate Interconnects; 3.5.1 Copper Interconnects; 3.5.1.1 Thermal-Compression Bonding. 
500 |a 3.5.1.2 Surface-Activated Bonding. 
506 |a Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty 
520 |a This book provides a comprehensive overview of the recent developments in advanced packaging. Established techniques are discussed, as well as emerging technologies, in order to provide readers with the most up-to-date developments. 
590 |a SpringerLink  |b Springer Complete eBooks 
650 0 |a Packaging  |x Materials. 
655 7 |a elektronické knihy  |7 fd186907  |2 czenas 
655 9 |a electronic books  |2 eczenas 
700 1 |a Lu, Daniel. 
700 1 |a Wong, C. P. 
776 0 8 |i Print version:  |a Lu, Daniel.  |t Materials for Advanced Packaging.  |d Cham : Springer International Publishing, ©2016  |z 9783319450971 
856 4 0 |u https://proxy.k.utb.cz/login?url=https://link.springer.com/10.1007/978-3-319-45098-8 
992 |c NTK-SpringerENG 
999 |c 99583  |d 99583 
993 |x NEPOSILAT  |y EIZ