Design and test technology for dependable systems-on-chip

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Bibliographic Details
Corporate Author IGI Global
Other Authors Ubar, Raimund, 1941-, Raik, Jaan, 1972-, Vierhaus, Heinrich Theodor, 1951-
Format eBook
LanguageEnglish
Published Hershey, Pa. : IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA), c2011.
Subjects
Systems on a chip > Design and construction.
Networks on a chip > Design and construction.
Systems on a chip > Testing.
Networks on a chip > Testing.
elektronické knihy
electronic books
Online AccessFull text
ISBN9781609602147
9781609602123
Physical Description1 online zdroj (1 v.)
Also available in print.

Cover

Table of Contents:
  • 1. System-level design of NoC-based dependable embedded systems / Mihkel Tagel, Peeter Ellervee, Gert Jervan
  • 2. Synthesis of flexible fault-tolerant schedules for embedded systems with soft and hard timing constraints / Viacheslav Izosimov ... et al.
  • 3. Optimizing fault tolerance for multi-processor system-on-chip / Dimitar Nikolov ... et al.
  • 4. Diagnostic modeling of digital systems with multi-level decision diagrams / Raimund Ubar ... et al.
  • 5. Enhanced formal verification flow for circuits integrating debugging and coverage analysis / Daniel Grosse, Görschwin Fey, Rolf Drechsler
  • 6. Advanced technologies for transient faults detection and compensation / Matteo Reorda, Luca Sterpone, Massimo Violante
  • 7. Memory testing and self-repair / Mária Fischerová, Elena Gramatová
  • 8. Fault-tolerant and fail-safe design based on reconfiguration / Hana Kubatova, Pavel Kubalik
  • 9. Self-repair technology for global interconnects on SoCs / Daniel Scheit, Heinrich Vierhaus
  • 10. Built-in self repair for logic structures / Tobias Koal, Heinrich Vierhaus.
  • 11. Self-repair by program reconfiguration in VLIW processor architectures / Mario Schölzel, Pawel Pawlowski, Adam Dabrowski
  • 12. Fault simulation and fault injection technology based on SystemC / Silvio Misera, Roberto Urban
  • 13. High-level decision diagram simulation for diagnosis and soft-error analysis / Jaan Raik ... et al.
  • 14. High-speed logic level fault simulation / Raimund Ubar, Sergei Devadze
  • 15. Software-based self-test of embedded microprocessors / Paolo Bernardi ... et al.
  • 16. SoC self test based on a test-processor / Tobial Koal, Rene Kothe, Heinrich Vierhaus
  • 17. Delay faults testing / Marcel Baláž, Roland Dobai, Elena Gramatová
  • 18. Low power testing / Zdenek Kotásek, Jaroslav Škarvada
  • 19. Thermal-aware SoC test scheduling / Zhiyuan He, Zebo Peng, Petru Eles
  • 20. Study on combined test-data compression and test planning for testing of modular SoCs / Anders Larsson ... et al.
  • 21. Reduction of the transferred test data amount / Ondrej Novák
  • 22. Sequential test set compaction in LFSR reseeding / Artur Jutman, Igor Aleksejev, Jaan Raik.

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