Design and test technology for dependable systems-on-chip
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| Corporate Author | |
|---|---|
| Other Authors | , , |
| Format | eBook |
| Language | English |
| Published |
Hershey, Pa. :
IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA),
c2011.
|
| Subjects | |
| Online Access | Full text |
| ISBN | 9781609602147 9781609602123 |
| Physical Description | 1 online zdroj (1 v.) Also available in print. |
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| 020 | |a 9781609602147 |q (ebook) | ||
| 020 | |z 9781609602123 | ||
| 024 | 7 | |a 10.4018/978-1-60960-212-3 |2 doi | |
| 035 | |a (OCoLC)707616682 | ||
| 040 | |a QE2 |b eng |c QE2 |d YDXCP |d OCLCQ |d UIU |d IGIGL |d OCLCQ |d OCLCO |d ZCU | ||
| 245 | 0 | 0 | |a Design and test technology for dependable systems-on-chip |h [elektronický zdroj] / |c Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors. |
| 260 | |a Hershey, Pa. : |b IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA), |c c2011. | ||
| 300 | |a 1 online zdroj (1 v.) | ||
| 504 | |a Includes bibliographical references. | ||
| 505 | 0 | |a 1. System-level design of NoC-based dependable embedded systems / Mihkel Tagel, Peeter Ellervee, Gert Jervan -- 2. Synthesis of flexible fault-tolerant schedules for embedded systems with soft and hard timing constraints / Viacheslav Izosimov ... et al. -- 3. Optimizing fault tolerance for multi-processor system-on-chip / Dimitar Nikolov ... et al. -- 4. Diagnostic modeling of digital systems with multi-level decision diagrams / Raimund Ubar ... et al. -- 5. Enhanced formal verification flow for circuits integrating debugging and coverage analysis / Daniel Grosse, Görschwin Fey, Rolf Drechsler -- 6. Advanced technologies for transient faults detection and compensation / Matteo Reorda, Luca Sterpone, Massimo Violante -- 7. Memory testing and self-repair / Mária Fischerová, Elena Gramatová -- 8. Fault-tolerant and fail-safe design based on reconfiguration / Hana Kubatova, Pavel Kubalik -- 9. Self-repair technology for global interconnects on SoCs / Daniel Scheit, Heinrich Vierhaus -- 10. Built-in self repair for logic structures / Tobias Koal, Heinrich Vierhaus. | |
| 505 | 8 | |a 11. Self-repair by program reconfiguration in VLIW processor architectures / Mario Schölzel, Pawel Pawlowski, Adam Dabrowski -- 12. Fault simulation and fault injection technology based on SystemC / Silvio Misera, Roberto Urban -- 13. High-level decision diagram simulation for diagnosis and soft-error analysis / Jaan Raik ... et al. -- 14. High-speed logic level fault simulation / Raimund Ubar, Sergei Devadze -- 15. Software-based self-test of embedded microprocessors / Paolo Bernardi ... et al. -- 16. SoC self test based on a test-processor / Tobial Koal, Rene Kothe, Heinrich Vierhaus -- 17. Delay faults testing / Marcel Baláž, Roland Dobai, Elena Gramatová -- 18. Low power testing / Zdenek Kotásek, Jaroslav Škarvada -- 19. Thermal-aware SoC test scheduling / Zhiyuan He, Zebo Peng, Petru Eles -- 20. Study on combined test-data compression and test planning for testing of modular SoCs / Anders Larsson ... et al. -- 21. Reduction of the transferred test data amount / Ondrej Novák -- 22. Sequential test set compaction in LFSR reseeding / Artur Jutman, Igor Aleksejev, Jaan Raik. | |
| 520 | 3 | |a Covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). | |
| 530 | |a Also available in print. | ||
| 590 | |a Knovel Library |b ACADEMIC - Electronics & Semiconductors | ||
| 506 | |a Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty univerzity | ||
| 650 | 0 | |a Systems on a chip |x Design and construction. | |
| 650 | 0 | |a Networks on a chip |x Design and construction. | |
| 650 | 0 | |a Systems on a chip |x Testing. | |
| 650 | 0 | |a Networks on a chip |x Testing. | |
| 655 | 7 | |a elektronické knihy |7 fd186907 |2 czenas | |
| 655 | 9 | |a electronic books |2 eczenas | |
| 700 | 1 | |a Ubar, Raimund, |d 1941- | |
| 700 | 1 | |a Raik, Jaan, |d 1972- | |
| 700 | 1 | |a Vierhaus, Heinrich Theodor, |d 1951- | |
| 710 | 2 | |a IGI Global. | |
| 776 | 1 | |c Original |w (DLC) 2010045850 | |
| 776 | 0 | 8 | |i Print version: |z 1609602129 |z 9781609602123 |w (DLC) 2010045850 |
| 856 | 4 | 0 | |u https://proxy.k.utb.cz/login?url=http://app.knovel.com/hotlink/toc/id:kpDTTDSC01/design_and_test_technology_for_dependable_systemsonchip |
| 992 | |a BK |c KNOVEL | ||
| 999 | |c 78987 |d 78987 | ||
| 993 | |x NEPOSILAT |y EIZ | ||