A designer's guide to asynchronous VLSI
"Bypass the limitations of synchronous design and create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. The fundamentals of asynchronous design are covered, as is a large variety of design styles, while the emphasis throughout...
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| Main Author | |
|---|---|
| Other Authors | , |
| Format | eBook |
| Language | English |
| Published |
Cambridge ; New York :
Cambridge University Press,
2010.
|
| Subjects | |
| Online Access | Full text |
| ISBN | 9780511675492 9780511672248 9780511670176 9780521872447 |
| Physical Description | 1 online zdroj (xii, 339 p.) : ill. |
Cover
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| 100 | 1 | |a Beerel, Peter A. | |
| 245 | 1 | 2 | |a A designer's guide to asynchronous VLSI |h [elektronický zdroj] / |c Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti. |
| 260 | |a Cambridge ; |a New York : |b Cambridge University Press, |c 2010. | ||
| 300 | |a 1 online zdroj (xii, 339 p.) : |b ill. | ||
| 520 | |a "Bypass the limitations of synchronous design and create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. The fundamentals of asynchronous design are covered, as is a large variety of design styles, while the emphasis throughout is on practical techniques and real-world applications"--Provided by publisher. | ||
| 520 | |a "This book provides an introduction to this diverse area of VLSI from a designer's point of view. Our goal is to enable designers to appreciate the many asynchronous design choices that may be readily available in the near future"--Provided by publisher. | ||
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | |a Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith. | |
| 590 | |a Knovel Library |b ACADEMIC - Computer Hardware Engineering | ||
| 506 | |a Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty univerzity | ||
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Computer-aided design. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Design and construction. | |
| 655 | 7 | |a elektronické knihy |7 fd186907 |2 czenas | |
| 655 | 9 | |a electronic books |2 eczenas | |
| 700 | 1 | |a Ozdag, Recep O. | |
| 700 | 1 | |a Ferretti, Marcos. | |
| 776 | 0 | 8 | |i Print version: |a Beerel, Peter A. |t Designer's guide to asynchronous VLSI. |d Cambridge ; New York : Cambridge University Press, 2010 |z 9780521872447 |w (DLC) 2009042290 |w (OCoLC)459209613 |
| 856 | 4 | 0 | |u https://proxy.k.utb.cz/login?url=http://app.knovel.com/hotlink/toc/id:kpDGAVLSIA/designers_guide_to_asynchronous_vlsi |
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