rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: ASIC and FPGA verification
    sub title: a guide to component modeling
  name:
    name part: Munden, Richard.
    role:
      role term: creator
  type of resource: text
  genre: elektronické knihy
  genre: electronic books
  origin info:
    place:
      place term: cau
    place:
      place term: San Francisco, Calif
    publisher: Morgan Kaufmann
    date issued: ©2005
    date issued: 2005
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: electronic
    form: elektronický zdroj
    form: remote
    extent: 1 online zdroj (1 volume).
  abstract: Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.
  table of contents: 1. Introduction to Board-Level Verification; 2. Tour of a simple model; 3. VHDL packages for component models; 4. Introduction to SDF; 5. Anatomy of a VITAL Model; 6. Modeling Delays; 7. VITAL truth tables; 8. Modeling timing constraints; 9. Modeling registered devices; 10. Conditional delays and timing constraints; 11. Negative timing constraints; 12. Timing Files and Backannotation; 13. Adding Timing to Your RTL Code; 14. Modeling Memories; 15. Considerations for Component Modeling; 16. Modeling Component Centric Features; 17. Testbenches for Component Models.
  target audience: specialized
  note: Richard Munden.
  note: Includes index.
  note: Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty univerzity
  subject:
    topic: Application-specific integrated circuits
  related item:
    title info:
      title: ASIC and FPGA verification
    name:
      name part: Munden, Richard.
    origin info:
      publisher: San Francisco, Calif. : Morgan Kaufmann, ©2005
    identifier: (OCoLC)56642597
  related item:
    title info:
      title: Morgan Kaufmann series in systems on silicon
  identifier: 9781417549719
  identifier: 9780125105811
  identifier: 9780080475929
  identifier: https://proxy.k.utb.cz/login
  access condition: Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty univerzity
  record info:
    record content source: N$T
    record creation date: 041028
    record change date: 20251006170653.0
    record identifier: 78159
    language of cataloging:
      language term: eng