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LEADER |
01763cam a2200457 a 4500 |
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65577 |
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CZ ZlUTB |
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20240829151139.0 |
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091120s2010 xxua b 001 0 eng |
020 |
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|a 9780262014335
|q (váz.)
|
035 |
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|a (OCoLC)ocn468853962
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|a DLC
|c DLC
|d YDXCP
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|d C#P
|d BWX
|d CDX
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|d ZLD002
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|
7 |
|a 621.38
|x Elektronika
|2 Konspekt
|9 19
|
080 |
|
|
|a 621.38.011.7
|2 MRF
|
080 |
|
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|a 004.438VHDL
|2 MRF
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|a 004.436.2
|2 MRF
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|a 004.94
|2 MRF
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|a (035)
|2 MRF
|
100 |
1 |
|
|a Pedroni, Volnei A.
|7 stk2008441689
|4 aut
|
245 |
1 |
0 |
|a Circuit design and simulation with VHDL /
|c Volnei A. Pedroni
|
250 |
|
|
|a 2nd ed.
|
260 |
|
|
|a Cambridge, Mass. :
|b MIT Press,
|c c2010
|
300 |
|
|
|a xix, 608 s. :
|b il. ;
|c 24 cm
|
500 |
|
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|a Rev. vyd.: Circuit design with VHDL / Volnei A. Pedroni. 2004
|
504 |
|
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|a Obsahuje bibliografii a rejstřík
|
650 |
0 |
7 |
|a elektronické obvody
|7 ph114450
|2 czenas
|
650 |
0 |
7 |
|a VHDL (programovací jazyk)
|7 ph137700
|2 czenas
|
650 |
0 |
7 |
|a popisné jazyky hardwaru
|7 ph137720
|2 czenas
|
650 |
0 |
7 |
|a modelování a simulace
|7 ph125543
|2 czenas
|
650 |
0 |
9 |
|a electronic circuits
|2 eczenas
|
650 |
0 |
9 |
|a VHDL
|2 eczenas
|
650 |
0 |
9 |
|a computer hardware description languages
|2 eczenas
|
650 |
0 |
9 |
|a modeling and simulation
|2 eczenas
|
655 |
|
7 |
|a příručky
|7 fd133209
|2 czenas
|
655 |
|
9 |
|a handbooks, manuals, etc
|2 eczenas
|
700 |
1 |
|
|a Pedroni, Volnei A.
|t Circuit design with VHDL
|
910 |
|
|
|a ZLD002
|
992 |
|
|
|a BK
|b SK
|d 1
|
999 |
|
|
|c 65577
|d 65577
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|0 0
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|6 62138PEDRONIVA
|7 0
|8 BOOK
|9 118646
|a UTBZL
|b UTBZL
|c 006
|d 2012-08-17
|l 1
|o 621.38/PEDRONI,V.A.
|p 420010146068
|r 2021-09-21
|v 1409.00
|w 2019-08-26
|x N:nákup; Převod FAI: Erik Král, 21.9.2021
|x 20100831
|y 04
|