Emerging technology and architecture for big-data analytics

This book describes the current state of the art in big-data analytics, from a technology and hardware architecture perspective. The presentation is designed to be accessible to a broad audience, with general knowledge of hardware design and some interest in big-data analytics. Coverage includes eme...

Full description

Saved in:
Bibliographic Details
Other Authors Chattopadhyay, Anupam (Editor), Chang, Chip-Hong (Editor), Yu, Hao (Electrical engineer) (Editor)
Format Electronic eBook
LanguageEnglish
Published Cham, Switzerland : Springer, 2017.
Subjects
Big data.
elektronické knihy
electronic books
Online AccessFull text
ISBN9783319548401
9783319548395
Physical Description1 online resource (xi, 330 pages) : illustrations (some color)

Cover

LEADER 00000cam a2200000Ii 4500
001 100027
003 CZ-ZlUTB
005 20251008112006.0
006 m o d
007 cr cnu|||unuuu
008 170424s2017 sz a ob 000 0 eng d
040 |a N$T  |b eng  |e rda  |e pn  |c N$T  |d GW5XE  |d EBLCP  |d YDX  |d UAB  |d N$T  |d MERER  |d ESU  |d AZU  |d UPM  |d OCLCF  |d OCLCQ  |d OCLCO  |d VT2  |d OTZ  |d OCLCQ  |d IOG  |d U3W  |d CAUOI  |d KSU  |d WYU  |d UKMGB  |d AUD  |d UKAHL  |d OCLCQ  |d ERF  |d UKBTH  |d LEATE  |d OCLCQ  |d SFB  |d OCLCQ 
020 |a 9783319548401  |q (electronic bk.) 
020 |z 9783319548395  |q (print) 
024 7 |a 10.1007/978-3-319-54840-1  |2 doi 
035 |a (OCoLC)983797035  |z (OCoLC)984206223  |z (OCoLC)984591224  |z (OCoLC)985233428  |z (OCoLC)985383871  |z (OCoLC)985483898  |z (OCoLC)985635773  |z (OCoLC)985760776  |z (OCoLC)986062443  |z (OCoLC)986462058  |z (OCoLC)986610733  |z (OCoLC)986872204  |z (OCoLC)988381546  |z (OCoLC)999514827  |z (OCoLC)1005756787  |z (OCoLC)1011955230  |z (OCoLC)1036266703  |z (OCoLC)1048171404  |z (OCoLC)1066592185  |z (OCoLC)1086473268  |z (OCoLC)1112523039  |z (OCoLC)1112980944  |z (OCoLC)1113393028  |z (OCoLC)1116145964  |z (OCoLC)1122846922  |z (OCoLC)1127187652 
245 0 0 |a Emerging technology and architecture for big-data analytics /  |c Anupam Chattopadhyay, Chip Hong Chang, Hao Yu, editors. 
264 1 |a Cham, Switzerland :  |b Springer,  |c 2017. 
300 |a 1 online resource (xi, 330 pages) :  |b illustrations (some color) 
336 |a text  |b txt  |2 rdacontent 
337 |a počítač  |b c  |2 rdamedia 
338 |a online zdroj  |b cr  |2 rdacarrier 
505 0 |a Preface; Contents; About the Editors; Part I State-of-the-Art Architectures and Automation for Data-Analytics; 1 Scaling the Java Virtual Machine on a Many-Core System; 1.1 Introduction; 1.2 Background; 1.2.1 Workload Selection; 1.2.2 Performance Analysis Tools; 1.2.3 Experimental Setup; 1.3 Thread-Local Data Objects; 1.4 Memory Allocators; 1.5 Java Concurrency API; 1.6 Garbage Collection; 1.7 Non-uniform Memory Access (NUMA); 1.8 Conclusion and Future Directions; Appendix; References; 2 Accelerating Data Analytics Kernels with HeterogeneousComputing; 2.1 Introduction; 2.2 Motivation. 
505 8 |a 2.3 Automated Design Space Exploration Flow2.3.1 The Lin-Analyzer Framework; 2.3.2 Framework Overview; 2.3.3 Instrumentation; 2.3.4 Optimized DDDG Generation; 2.3.4.1 Sub-trace Extraction; 2.3.4.2 DDDG Generation & Pre-optimizations; 2.3.5 DDDG Scheduling; 2.3.6 Enabling Design Space Exploration; 2.4 Acceleration of Data Analytics Kernels; 2.4.1 Estimation Accuracy; 2.4.1.1 Loop Unrolling and Loop Pipelining; 2.4.1.2 Array Partitioning; 2.4.2 Rapid Design Space Exploration; 2.5 Conclusion; References. 
505 8 |a 3 Least-squares-solver Based Machine Learning Acceleratorfor Real-time Data Analytics in Smart Buildings3.1 Introduction; 3.2 IoT System Based Smart Building; 3.2.1 Smart-Grid Architecture; 3.2.2 Smart Gateway for Real-Time Data Analytics; 3.2.3 Problem Formulation for Data Analytics; 3.3 Background on Neural Network Based Machine Learning; 3.3.1 Backward Propagation for Training; 3.3.2 Least-Squares Solver for Training; 3.3.3 Feature Extraction with Behavior Cognition; 3.4 Least-Squares Solver Based Training Algorithm; 3.4.1 Regularized 2-Norm; 3.4.2 Square-Root-Free Cholesky Decomposition. 
505 8 |a 3.4.3 Incremental Least-Squares Solution3.5 Least-Squares Based Machine Learning Accelerator Architecture; 3.5.1 Overview of Computing Flow and Communication; 3.5.2 FPGA Accelerator Architecture; 3.5.3 2-Norm Solver; 3.5.4 Matrix-Vector Multiplication; 3.6 Experiment Results; 3.6.1 Experiment Setup and Benchmark; 3.6.2 FPGA Design Platform and CAD Flow; 3.6.3 Scalable and Parameterized Accelerator Architecture; 3.6.4 Performance for Data Classification; 3.6.5 Performance for Load Forecasting; 3.6.6 Performance Comparisons with Other Platforms; 3.7 Conclusion; References. 
505 8 |a 4 Compute-in-Memory Architecture for Data-Intensive Kernels4.1 Introduction; 4.2 Malleable Hardware Acceleration; 4.2.1 Hardware Architecture; 4.2.2 Application Mapping; 4.2.2.1 Application Description Using an Instruction Set Architecture; 4.2.2.2 Application Mapping to the General Framework; 4.2.3 Domain Customization for Efficient Acceleration; 4.3 Case Studies for Memory-Centric Computing; 4.3.1 MAHA for Security Applications; 4.3.1.1 Domain Exploration; 4.3.1.2 Architecture Description; 4.3.1.3 Results and Comparison to Other Platforms; 4.3.2 MAHA for Text Mining Applications. 
506 |a Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty 
520 |a This book describes the current state of the art in big-data analytics, from a technology and hardware architecture perspective. The presentation is designed to be accessible to a broad audience, with general knowledge of hardware design and some interest in big-data analytics. Coverage includes emerging technology and devices for data-analytics, circuit design for data-analytics, and architecture and algorithms to support data-analytics. Readers will benefit from the realistic context used by the authors, which demonstrates what works, what doesn't work, and what are the fundamental problems, solutions, upcoming challenges and opportunities. Provides a single-source reference to hardware architectures for big-data analytics; Covers various levels of big-data analytics hardware design abstraction and flow, from device, to circuits and systems; Demonstrates how non-volatile memory (NVM) based hardware platforms can be a viable solution to existing challenges in hardware architecture for big-data analytics. 
504 |a Includes bibliographical references at the end of each chapters. 
590 |a SpringerLink  |b Springer Complete eBooks 
650 0 |a Big data. 
655 7 |a elektronické knihy  |7 fd186907  |2 czenas 
655 9 |a electronic books  |2 eczenas 
700 1 |a Chattopadhyay, Anupam,  |e editor. 
700 1 |a Chang, Chip-Hong,  |e editor. 
700 1 |a Yu, Hao  |c (Electrical engineer),  |e editor. 
776 0 8 |i Print version:  |t Emerging technology and architecture for big-data analytics.  |d Cham, Switzerland : Springer, 2017  |z 3319548395  |z 9783319548395  |w (OCoLC)971355364 
856 4 0 |u https://proxy.k.utb.cz/login?url=https://link.springer.com/10.1007/978-3-319-54840-1 
992 |c NTK-SpringerENG 
999 |c 100027  |d 100027 
993 |x NEPOSILAT  |y EIZ 

Similar Items